1. Technical Field
The present disclosure relates to integrated circuits comprising components distributed over several levels. Such integrated circuits comprise a stack of at least two semiconductor layers separated by an insulating layer. It is spoken of three-dimensional (3D) integration, and of 3D integrated circuits.
2. Discussion of the Related Art
Increasing the component density in integrated circuits generally is a constant concern. A solution is to manufacture integrated circuits comprising components distributed over several levels of semiconductor layers.
FIG. 1 is a cross-section view schematically showing an example of 3D integrated circuit comprising transistors distributed over two levels of semiconductor layers.
A silicon layer 1 of the lower level comprises MOS transistors T1, laterally insulated from one another, a single transistor being shown. Each transistor T1 comprises a gate 3 insulated from layer 1 by a gate insulator 5, and spacers 7 surrounding the gate. Source and drain regions 9 extend in layer 1 on either side of gate 3. A metal silicide layer 11 covers the upper surface of source and drain regions 9. Silicide layer 11 may also cover the lateral surfaces of the source and drain regions.
An insulating layer 15 separates silicon layer 1 from the lower level of another silicon layer 21 of the upper level. Like silicon layer 1, silicon layer 21 comprises MOS transistors T2, laterally insulated from one another, a single transistor being shown. Each transistor T2 comprises a gate 23 insulated from layer 21 by a gate insulator 25, spacers 27, and source and drain regions 29. A metal silicide layer 31 covers the upper surface of source and drain regions 29, and also possibly the lateral surfaces of these source and drain regions. An insulating layer 35 covers layer 21 and transistors T2.
In certain applications, the source or drain region of a transistor located on the upper level semiconductor layer is desired to be connected to the source or drain region of a transistor located on the lower level semiconductor layer. To achieve this, a via contacting the upper level semiconductor layer to the lower level semiconductor layer is desired to be formed.
FIGS. 2A and 2B are cross-section views schematically illustrating successive steps of a method for forming a via contacting two levels of semiconductor layers.
FIG. 2A illustrates a 3D structure of the type illustrated in FIG. 1 after the forming of an opening 41 providing access to upper level layer 21 and to lower level layer 1. Before the forming of opening 41, a previous masking step has been carried out to protect the regions which are not desired to be etched. Opening 41 has been formed by an anisotropic etching method, for example, by plasma etching. At the end of the etching, the bottom of opening 41 reaches a portion of silicide layer 11 covering lower level layer 1. The etching method is selected to selectively etch insulating layers 35, 15, but not silicon layer 21 covered with silicide 31. However, if upper level silicon layer 21 is very thin, for example, of a thickness much smaller than the thickness of insulating layer 15, layers 21, 31 risk, as illustrated, being partially or totally removed on forming of opening 41.
FIG. 2B illustrates the 3D structure after the filling of opening 41 with a conductive material 48. A via 49 contacting upper level layer 21 and lower level layer 1 is obtained. If upper level layer 21 has been totally removed at the previous step, the contact on layer 21 is taken only by lateral surface 46, 47 of layers 21, 31. The contact surface area is much smaller than if the contact was taken on the upper surface of layer 21 covered with silicide 31, and this all the more as layers 21, 31 are very thin. As a result, the electric contact between via 49 and the source or drain region of upper level layer 21 is not well established.
A solution to avoid the removal of upper level layers 21, 31 on forming of opening 41 comprises increasing the thickness of source and drain regions 29, after the forming of spacers 27 and before the forming of silicide layer 31, by local epitaxy. This however causes an increase in the stray capacitance between the gate and the source and drain regions of the upper level transistors, which is not desirable.